Traditional logic synthesis faces challenges of meeting the requirements demanded by the many emerging nanotech-nologies that are based on logic models different from standard CMOS. Several emerging nanodevices including Quantum-dot Cellular Automata (QCA) and Spin Torque Majority Gates (STMG) are based on majority logic. In addition, technology constraints require to restrict the number of fan-outs or impose difficulties in realizing inversions. In this paper, we use a majority-based logic synthesis approach to synthesize inversion-free networks with restricted fan-out. We propose one algorithm that propagates all inversions to the primary inputs and another algorithm that limits the number of fan-outs of each majority gate. These algorithms show significant impact on QCA- and STMG-based circuits. Experimental results demonstrate that the average area-delay-energy product can be improved by 3.1× in QCA-based circuits and from 2.9× to 8.1× for STMG-based circuits.