Soeken, Mathias
Gaillardon, Pierre-Emmanuel
De Micheli, Giovanni
RM3 based logic synthesis
Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)
Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)
Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)
Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)
logic synthesis
in-memory computing
majority logic
2017
2017-05-31
In-memory computing devices, such as resistive RAMs, natively implement material implication or a variant of the majority-of-three operation called RM<sub>3</sub>. This operation generalizes material implication and has been used as target operation in several logic synthesis algorithms for in-memory computing applications. In this work, we investigate a homogeneous logic network data structure that uses RM<sub>3</sub> as only logic operation. Such a data structure makes an ideal fit for the use in design automation algorithms for in-memory computing. We show how to derive RM<sub>3</sub> networks from well-known logic synthesis data structures and a technique how to obtain such networks using technology mapping.
IEEE
978-1-4673-6853-7
Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)
ERC Cybercare 669354 / SNF MAJesty 200021-169084 / SNF 200021-146600
Conference Papers
10.1109/ISCAS.2017.8050223