000233718 001__ 233718
000233718 005__ 20190317000910.0
000233718 020__ $$a978-1-4673-6853-7
000233718 0247_ $$a10.1109/ISCAS.2017.8050223$$2doi
000233718 037__ $$aCONF
000233718 245__ $$aRM3 based logic synthesis
000233718 260__ $$c2017-05-31$$bIEEE
000233718 269__ $$a2017-05-31
000233718 336__ $$aConference Papers
000233718 500__ $$aERC Cybercare 669354 / SNF MAJesty 200021-169084 / SNF 200021-146600
000233718 520__ $$aIn-memory computing devices, such as resistive RAMs, natively implement material implication or a variant of the majority-of-three operation called RM<sub>3</sub>. This operation generalizes material implication and has been used as target operation in several logic synthesis algorithms for in-memory computing applications. In this work, we investigate a homogeneous logic network data structure that uses RM<sub>3</sub> as only logic operation. Such a data structure makes an ideal fit for the use in design automation algorithms for in-memory computing. We show how to derive RM<sub>3</sub> networks from well-known logic synthesis data structures and a technique how to obtain such networks using technology mapping.
000233718 6531_ $$alogic synthesis
000233718 6531_ $$ain-memory computing
000233718 6531_ $$amajority logic
000233718 700__ $$g263922$$aSoeken, Mathias$$0249604
000233718 700__ $$aGaillardon, Pierre-Emmanuel
000233718 700__ $$g167918$$aDe Micheli, Giovanni$$0240269
000233718 7112_ $$dMay 28-31, 2017$$cBaltimore, Maryland, USA$$aIEEE International Symposium on Circuits and Systems (ISCAS)
000233718 773__ $$tProceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)
000233718 8560_ $$fcarole.burget@epfl.ch
000233718 8564_ $$uhttps://infoscience.epfl.ch/record/233718/files/08050223.pdf$$zn/a$$s98076$$yn/a
000233718 909C0 $$xU11140$$0252283$$pLSI1
000233718 909CO $$pIC$$qGLOBAL_SET$$ooai:infoscience.tind.io:233718$$pconf$$pSTI
000233718 917Z8 $$x112915
000233718 937__ $$aEPFL-CONF-233718
000233718 973__ $$rREVIEWED$$aEPFL
000233718 980__ $$aCONF