000233717 001__ 233717
000233717 005__ 20190317000910.0
000233717 020__ $$a978-1-4503-4972-7
000233717 0247_ $$a10.1145/3060403.3060432$$2doi
000233717 037__ $$aCONF
000233717 245__ $$aImproving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains
000233717 260__ $$c2017-05-12$$bACM$$aNew York, NY
000233717 269__ $$a2017-05-12
000233717 336__ $$aConference Papers
000233717 500__ $$aERC Cybercare 669354 / NSF China 61501268 / Zhejiang Provincial NSF LQ15F040001 / Ningbo City NSF 2015A610112
000233717 520__ $$aHard-wired carry chains in FPGAs are designed to improve efficiency of important arithmetic primitives. Although they are proven to be effective for arithmetic-rich functions, there are very few studies on the optimization opportunities of carry chains for general logic that is poor in arithmetic operations. Recently, Majority-Inverter Graphs (MIGs) were proposed for efficient Boolean logic optimization. MIGs open an opportunity for efficient mapping of critical paths onto hard carry chains, as the carry logic of a full adder is naturally a majority (MAJ) gate. In this paper, we propose an MIG-based synthesis method to exploit hard adders in FPGAs for the mapping of general logic. The proposed heuristic algorithm selects MAJ nodes to be mapped on the carry chains and the associated LUTs; then, the efficiency of carry chain mapping is examined theoretically for efficient LUT utilization. The experimental results show that, compared to traditional design flow Verilog-to-Routing (VTR 7.0), the proposed approach can improve delay by up to 25% with an average of 8%, while the channel width is reduced by up to 20% with an average of 6%.
000233717 6531_ $$aFPGA
000233717 6531_ $$amajority-inverter graph
000233717 6531_ $$acarry chain
000233717 6531_ $$atechnology mapping
000233717 700__ $$aChu, Zhufei
000233717 700__ $$g214644$$aTang, Xifan$$0247487
000233717 700__ $$g263922$$aSoeken, Mathias$$0249604
000233717 700__ $$g196536$$aPetkovska, Ana$$0245677
000233717 700__ $$g206309$$aZgheib, Grace$$0245678
000233717 700__ $$aAmarù, Luca
000233717 700__ $$aXia, Yinshui
000233717 700__ $$g101954$$aIenne, Paolo$$0241619
000233717 700__ $$g167918$$aDe Micheli, Giovanni$$0240269
000233717 700__ $$aGaillardon, Pierre-Emmanuel
000233717 7112_ $$dMay 10-12, 2017$$cBanff, Alberta, Canada$$aGreat Lakes Symposium on VLSI (GLVLSI)
000233717 773__ $$q131-136$$tProceedings of the Great Lakes Symposium on VLSI (GLVLSI)
000233717 8560_ $$fcarole.burget@epfl.ch
000233717 8564_ $$uhttps://infoscience.epfl.ch/record/233717/files/p131-chu.pdf$$zn/a$$s814920$$yn/a
000233717 909C0 $$xU11140$$0252283$$pLSI1
000233717 909C0 $$0252192$$pLAP$$xU10418
000233717 909CO $$qGLOBAL_SET$$pconf$$pSTI$$pIC$$ooai:infoscience.tind.io:233717
000233717 917Z8 $$x112915
000233717 917Z8 $$x112915
000233717 937__ $$aEPFL-CONF-233717
000233717 973__ $$rREVIEWED$$aEPFL
000233717 980__ $$aCONF