Clock jitter estimation in noise

Clock timing jitter refers to random perturbations in the sampling time in analog-to-digital converters (ADCs). The perturbations are caused by circuit imperfections in the sampling clock. This paper analyzes the effect of sampling clock jitter on the acquired samples in the midst of quantization noise and random Gaussian noise. The paper proposes a method for estimating the jitter for cognitive radio architectures at high sampling rates. The paper also examines the fixed- point implementation of the algorithm and its theoretical performance.


Published in:
IEEE International Symposium of Circuits and Systems (ISCAS), 1251-1254
Presented at:
IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, May 15-18, 2011
Year:
2011
Publisher:
IEEE
Laboratories:




 Record created 2017-12-19, last modified 2018-09-13


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