Sampling clock jitter estimation and compensation in ADC circuits

Clock timing jitters refer to random perturbations in the sampling time in analog-to-digital converters (ADCs). The perturbations are caused by circuit imperfections in the sampling clock. This paper analyzes the effect of sampling clock jitter on the acquired samples. The paper proposes two methods to estimate the jitter for superheterodyne receiver architectures and cognitive radio architectures at high sampling rates. The paper also proposes a method to compensate for the jitter. The methods are tested and validated via computer simulations and theoretical analysis.


Published in:
Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 829-832
Presented at:
IEEE International Symposium on Circuits and Systems - ISCAS 2010, Paris, France, May 30 - June 2, 2010
Year:
2010
Publisher:
IEEE
Laboratories:




 Record created 2017-12-19, last modified 2018-03-17


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