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000232616 005__ 20180913064600.0
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000232616 037__ $$aPATENT
000232616 245__ $$aSystem and Method for Optimization of Digital Circuits with Timing and Behavior Co-Designed by Introduction and Exploitation of False Paths
000232616 260__ $$c2017
000232616 269__ $$a2017
000232616 336__ $$aPatents
000232616 520__ $$aA digital circuit including a signal path with a false path, whereby the signal path includes at least 3 logic instances, the digital circuit further including a logic monitoring element for monitoring a part of the digital circuit, and for outputting a cut-back signal in case a determined risk of a full activation of the signal path is detected in the monitoring, wherein the signal path includes a logic cutting selector element as one of the 3 logic instances, the logic cutting selector element to be triggered by at least the cut-back signal to prevent the full activation of the signal path, the logic cutting selector element being configured to switch, the switching either maintaining the signal path itself, or preventing the full activation of the signal path by substituting it for an alternate signal path, thereby inducing the false path.
000232616 700__ $$0247954$$g214119$$aCamus, Vincent
000232616 700__ $$aSchlachter, Jérémy
000232616 700__ $$aEnz, Christian$$0240858$$g105059
000232616 909C0 $$0252085$$pTTO$$xU10021
000232616 909C0 $$xU12701$$0252498$$pICLAB
000232616 909CO $$pSTI$$ooai:infoscience.tind.io:232616
000232616 917Z8 $$x170628
000232616 937__ $$aEPFL-PATENT-232616
000232616 973__ $$aEPFL
000232616 980__ $$aPATENT