Negative Capacitance Field Effect Transistors; Capacitance Matching and non-Hysteretic Operation

This work experimentally demonstrates negative capacitance MOSFETs in hysteretic and non-hysteretic modes of operation. A PZT capacitor is externally connected to the gate of commercial nMOSFETs fabricated in 28nm CMOS technology to explore the negative capacitance effect. In hysteretic devices, subthreshold slope as steep as 10mV/dec is achieved in the region where the ferroelectric represents an S-shape polarization. In addition, a matching condition is achieved between a PZT capacitor and the gate capacitance of MOSFETs fabricated on SOI substrates. For the first time, we achieve a non-hysteretic switch configuration in our fabricated MOSFETs, suitable for analog and digital applications, for which a reduction in the subthreshold swing is obtained down to 20mV/dec.


Presented at:
Solid-State Device Research Conference (ESSDERC), 2017 47th European, Leuven, Belgium, 11-14 Sept. 2017
Year:
2017
Publisher:
Piscataway, IEEE
Laboratories:




 Record created 2017-10-21, last modified 2018-03-18

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