Electronic solutions for power system emulation

Nowadays electric power systems are subject to continuous changes and the needs in the power generation and delivery service are constantly increasing, with a higher complexity of a progressively more distributed network. Because the impact of a failure can have enormous economic consequences, the security of the power transfer becomes the key element that needs to be constantly screened during operation. This suggests a complete renewal of the available stability analysis tools targeting the ability to operate online. In this context, transient stability analysis (TSA) has been recognized as a major computing challenge. Existing digital solutions encounter speed limitations and suffer significantly from the growing system size. Particularly burdensome in terms of computations is the solving of the system nodal matrix equation of the transmission system. A study of the potential of an application dedicated computational strategy based on mixed-signal architecture is presented in this work. It relies on the emulation of the transmission system by using analog electronic components. From a theoretical point of view, the laws of physics governing such an electronic system ensure that an instantaneous solution of the stated problem can be obtained. The first part of this thesis focuses on the description of a fully operational discrete electronics hardware prototype. Its efficiency in solving the TSA problem was analyzed for typical power system test cases in terms of speed and accuracy. The solution was further tuned by developing an optimized system architecture based on an application specific integrated circuit (ASIC). The hardware size reduction is the major motivation for this development as it becomes critical for the analysis of large power systems. These developments revealed two concerns of utmost importance. The results obtained using the first platform highlighted that the TSA is sensitive to the limited accuracy of the hardware components. In addition, the ASIC design underlined the difficulty to solve this issue when the speed of operations and a low circuit complexity are also aimed for. The second point is associated with the analog solver speed. The theoretical efficiency of the proposed solution is hampered by non-negligible circuit parasitic capacitances. The reprogrammable parts of the circuit contribute to a large extend to these parasitic elements. Hence, highly reconfigurable architectures suffer from higher speed limitations. To sum up, this work shows that the translation of the power system analog emulation principle into an operating, flexible and programmable circuit system raises major concerns that are closely associated to the resolution speed and accuracy. The research conducted in this thesis has been oriented towards the development of an engine targeting minimum circuit complexity, in order to make it practical for extensions of the tool capacity to larger system sizes. Although there is a potential to improve the described resolution speed limitation, the complexity of such a next generation system might provide an uncompetitive solution with regards to existing alternatives, from a cost, accuracy, system size and flexibility perspective.


Advisor(s):
Kayal, Maher
Year:
2017
Publisher:
Lausanne, EPFL
Keywords:
Other identifiers:
urn: urn:nbn:ch:bel-epfl-thesis7761-7
Laboratories:


Note: The status of this file is: EPFL only


 Record created 2017-09-20, last modified 2019-12-05

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