Design and Modeling of Serial Data Transceiver Architecture by Employing Multi-Tone Single-Sideband Signaling Scheme

This paper presents the design and analysis of a serial link transceiver (TRX) architecture employing analog multi-tone (AMT) signaling for chip-to-chip communication. Multi-tone single-sideband (SSB) signaling scheme is proposed in TRX architecture in order to optimize bandwidth requirements for each sub-channel and to improve signal-to-noise ratio (SNR) by reducing inter-channel interferences (ICI) between neighbouring sub-channels. System-level modeling results show that the proposed TRX architecture enables equalizer-free communication at 16 Gb/s over a lossy backplane channel that exhibits 22 dB attenuation at 8 GHz, while conventional NRZ signaling TRX necessitates a two-stage continuous-time linear equalizer (CTLE). A channel frequency-response inversion scheme, the up/downconversion mechanism of the TX/RX data stream and the RX design considerations have been analyzed and investigated by architectural modeling.

Published in:
IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 64, 12, 3192-3201
Piscataway, Ieee-Inst Electrical Electronics Engineers Inc

 Record created 2017-08-09, last modified 2018-09-13

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