A DAC Assisted Speed Enhancement Technique for High Resolution SAR ADC

In this paper, a technique aiming at enhancing the conversion speed of asynchronous high resolution SAR ADCs is presented. In conventional SAR ADCs, the capacitive DAC size is growing exponentially with the converter resolution. The settling time of the MSB capacitors get thus longer, limiting the total conversion speed. This method proposes to operate a small and fast 3-bit ADC in parallel with the main one to determine rapidly the MSB values, while the capacitors of the main DAC have not settled yet. An error correction circuit detects and corrects automatically any decision error due to mismatch between the two DACs. A design example of a 10-bit ADC is implemented in 28nm FDSOI CMOS technology to illustrate this technique. A sampling rate of 800MS/s is achieved without any effort for reducing the capacitive DAC size.

Presented at:
Ph.D Research in Microelectronics and Electronics (PRIME), Giardini Naxos - Taormina, Italy, June 12-15, 2017

 Record created 2017-06-27, last modified 2018-03-17

Rate this document:

Rate this document:
(Not yet reviewed)