This research presents a high-speed hardware platform dedicated to emulate electrical power networks for the fault location. The solution implements an algorithm based on the Electromagnetic Time-Reversal (EMTR) principle, which allows locating faults in various network types and topologies. Although the technique is highly robust and accurate, its processing is complex and time consuming if solved with classical digital approaches. Therefore, a dedicated computation platform optimized on the processing speed was developed in order to allow its real-time implementation and make it compatible with smart-grids. Two different power network modelling approaches are presented. The first one is based on a finite element representation of the distributed parameters transmission line. The lossless line, initially characterized by a per-unit length inductance and capacitance, is replaced by a series of identical ladder connected inductor-capacitor (LC) elements. The second model is based on the general solution of the telegrapher's equations describing the signals propagated along the transmission line. In this method, the travelling waves' propagation taking place in the line is simulated with cascaded discrete-time delay elements. A possible implementation by means of analog circuits is then presented for each line model. The discretized parameters LC line is simulated by transconductance-capacitor, also called gyrator-C or gm-C topologies, more suitable for microelectronic implementation. On the other hand, the discrete-time delay element of the second method is implemented by switched-capacitor (SC) circuits. The processing time associated to each method can be scaled down according to the microelectronic parameters of the LC line, or by increasing the sampling frequency of the discrete-time model. Through this time scaling, the hardware emulation allows a fault location within duration of up to a hundred times shorter than with classical digital implementations of similar accuracy. The impact of non-ideal effects associated to the microelectronic implementation, such as the CMOS active elements finite gain, offset and dynamic range, or the switched-capacitor charge injection, etc., is evaluated for each model. Associated design constraints are then derived in order to ensure a given fault location accuracy, similarly to that of classical digital methods. Since the switched-capacitor model is characterized by higher robustness and accuracy than the LC line, it is therefore preferred for a silicon implementation. Results obtained after a CMOS AMS 0.35um process implementation have shown that the discrete-time model allows a fault location within 160ms, versus 6s in a classical digital method, with similar resolution (1%). The speed improvement obtained through the presented method is essential, potentially allowing real-time fault management in power grids. Finally, the impact of the magnitude quantization on the line model, offering perspectives of full digital implementations, is evaluated. A possible extension of the model for the simulation of interconnected or multi-conductor lines is also discussed.