Non-LUT field-programmable gate arrays

New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is a tree structure comprised of a number of levels of cells with each cell consisting of a logic gate or the functional equivalent of a logic gate, one or more selectable inverters, and wherein the inputs of the logic block consist of the inputs to the logic gate or functional equivalent of the logic gate and inputs to the selectable inverters. The new logic blocks can map circuits more efficiently than LUTs, because they include multi-output blocks and can cover more logic depth due to the higher input and output bandwidth.

Other identifiers:
EPO Family ID: 51934997
EPO Family ID: 48653901
TTO: 6.1138

 Record created 2017-05-24, last modified 2018-01-28

Rate this document:

Rate this document:
(Not yet reviewed)