Cmos compatible non-volatile latch and d-flip flop using resistive switching materials

A non-volatile latch circuitry, comprising a Re RAM cell configured to store a final value of the non-volatile latch circuitry; a data selection circuitry configured to connect or disconnect a data input to a plus voltage node and a minus voltage node of the Re Ram cell depending on a clock input voltage level; a pull down transistor configured to set a first voltage level at the minus voltage node to a logically low voltage level if the data input is not connected to the plus and minus voltage nodes of the Re RAM cell; a bias circuitry configured to provide a fix bias current to set a second voltage level at the plus voltage node to a varying voltage level depending on the resistor value of the Re RAM cell if the data input is not connected to the plus voltage node; and a threshold adjusted circuitry arranged to convert an analog value of the second voltage level into a digital value and configured to generate an output signal and / or an inverted output signal.

Other identifiers:
EPO Family ID: 50980337
TTO: 6.1290
Patent number(s):

 Record created 2017-05-24, last modified 2018-03-17

Rate this document:

Rate this document:
(Not yet reviewed)