Pattern-based fpga logic block and clustering algorithm
Tang, Xifan; Gaillardon, Pierre-emmanuel Julien Marc; De Micheli, Giovanni
2016

Abstract

A routing architecture for fast interconnections between Look-Up Tables (LUTs) in a group of Basic Logic Elements (BLEs), whereby a size of the group ranges from 1 to k+1, where k is the number of inputs of a LUT, and LUTs in the group are indexed from 1 to k+1, and whereby (a) an output of a LUTi, 1≦̸i≦̸k, connects to one of the inputs of routing multiplexers of LUTj, i

Details

Title Pattern-based fpga logic block and clustering algorithm
Author(s) Tang, Xifan ; Gaillardon, Pierre-emmanuel Julien Marc ; De Micheli, Giovanni
Date 2016
Keywords
Other identifier(s) EPO Family ID: 55402789
Patent number(s) US9971862 (B2)
US2016063168 (A1)
Laboratories TTO
LSI1
LSI2
Record Appears in Scientific production and competences > STI - School of Engineering > IEM - Institut d'Electricité et de Microtechnique > LSI2 - Integrated Systems Laboratory (STI/IC)
Scientific production and competences > I&C - School of Computer and Communication Sciences > IINFCOM > LSI1 - Integrated Systems Laboratory 1 (STI/IC)
Scientific production and competences > Non-academic units > TTO - Technology Transfer Office
Work produced at EPFL
Patents
Record creation date 2017-05-11

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