Journal article

Classification of Resilience Techniques Against Functional Errors at Higher Abstraction Layers of Digital Systems

Nano-scale technology nodes bring reliability concerns back to the center stage of digital system design. A systematic classification of approaches that increase system resilience in presence of functional hardwareinduced errors is presented, dealing with higher system abstractions: i.e. the (micro-) architecture, the mapping and platform software. The field is surveyed in a systematic way based on non-overlapping categories, which add insight into the ongoing work by exposing similarities and differences. Hardware and software solutions are discussed in a similar fashion, so that interrelationships become apparent. The presented categories are illustrated by representative literature examples to illustrate their properties. Moreover, it is demonstrated how hybrid schemes can be decomposed into their primitive components.

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