A 60 Gb/s 1.9 pJ/bit NRZ Optical-Receiver with Low Latency Digital CDR in 14nm CMOS FinFET

This work reports a low power implementation of a 60Gb/s NRZ optical receiver (RX) in 14nm bulk CMOS finFET featuring a first-order digital CDR with high jitter tolerance (JTOL). The design includes a single phase-rotator (PR) with low complexity control logic suitable for high-speed applications. Multi-phase clock signals that drive data/edge slicers are created by an open loop-quadrature clock generator. The circuit, characterized in an 850nm VCSEL based optical link, recovers PRBS7 data (BER<10E-12) at 60Gb/s. At this data rate, the CDR achieves +/- 600ppm frequency tracking range. The measured sinusoidal JTOL indicates a corner frequency of about 80MHz, with high frequency JTOL of 0.16UIpp at -5dBm optical modulation amplitude (OMA). The RX energy efficiency is 1.9pJ/bit.

Published in:
Proceedings of the 2017 Symposium on VLSI Circuits
Presented at:
2017 Symposium on VLSI Circuits, Kyoto, Japan, June 5-8, 2017

 Record created 2017-04-25, last modified 2018-09-13

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