A Single-chip 2048x1080 Resolution 32fps 380mW Trinocular Disparity Estimation Processor in 28nm CMOS Technology

This paper presents a single-chip trinocular disparity estimation processor, capable of computing in real-time up to 2048×1080 resolution depth maps at 32fps with up to 256-pixel disparity range using two/three CMOS camera sensors. The most important feature of the presented design is that the chip is based on a trinocular adaptive window matching process that requires very limited on-chip memory, and completely avoids the usage of any external memory. Moreover, it provides the highest reported disparity range capability at the lowest power consumption and highest frame rate, while computing high quality disparity results. It features a stream-in/out interface to be easily integrated in existing vision systems, without additional overhead, and offers a dynamically scalable tradeoff between throughput, resolution and disparity range. The single-chip is fabricated in 28nm CMOS technology, has a die area of 5.96mm2 and a power consumption of 380mW at 300MHz clock frequency.

Published in:
Proceedings of the 2017 Symposium on VLSI Circuits
Presented at:
2017 Symposium on VLSI Circuits, Kyoto, Japan, June 5-8, 2017

 Record created 2017-03-30, last modified 2019-08-12

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