Benchmarking of Homojunction Strained-Si NW Tunnel FETs for Basic Analog Functions

This paper reports a compact ambipolar model for homojunction strained-silicon (sSi) nanowire (NW) tunnel FETs (TFETs) capable of accurately describing both I-V and G-V characteristics in all regimes of operation, n- and p-ambipolarity, the superlinear onset of the output characteristics, and the temperature dependence. Experimental calibration on long channel (350 nm) complementary n- and p-type sSi NW TFETs has been performed to create the model, which is used to systematically benchmark the main analog figures of merit at device level: g(m)/I-d, g(m)/g(ds), f(T) and f(T)/IdVd, and their temperature dependence from 25 degrees C to 125 degrees C. This allows for a direct comparison between 28-nm low-power Fully Depleted Silicon on Insulator (FD-SOI) CMOS node and 28-nm double-gate (DG) TFET. We demonstrate unique advantages of sSi DG TFET over CMOS, in terms of: 1) reduced temperature dependence of subthreshold swing; 2) higher transconductance per unit of current with peaks close to 40 V-1, for currents lower than 10 nA/mu m; and 3) higher unity gain frequency per unit power for currents below 10 nA/mu m.

Published in:
IEEE Transactions on Electron Devices, 1-8
Piscataway, Institute of Electrical and Electronics Engineers

 Record created 2017-03-02, last modified 2018-03-17

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