Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

This paper proposes a novel approach to modeling of gate level timing errors during high-level instruction set simulation. hi contrast to conventional, purely random fault injection, our physically motivated approach directly relates to the underlying circuit structure, hence allowing for a significantly more detailed characterization of application performance under scaled frequency / voltage (including supply noise). The model uses gate level timing statistics extracted by dynamic timing analysis from the post place & route netlist of a general-purpose processor to perform instruction aware fault injections. We employ a 28 nm OpenRISC core as a case study, to demonstrate how statistical fault injection provides a more accurate and realistic analysis of power vs. error performance.


Published in:
2016 53Rd Acm/Edac/Ieee Design Automation Conference (Dac)
Presented at:
53rd ACM/EDAC/IEEE Design Automation Conference (DAC), Austin, TX, JUN 05-09, 2016
Year:
2016
Publisher:
New York, Ieee
ISSN:
0738-100X
ISBN:
978-1-4503-4236-0
Laboratories:




 Record created 2017-01-24, last modified 2019-08-12


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