A 51.4 Mb/s FSK Transmitter Employing a Phase Domain Digital Synthesizer with 1.5 mu s Start-up for Energy Efficient Duty Cycling

This paper presents a low start-up latency Transmitter (TX) that can achieve FSK data rates of upto 51.4 Mb/s for deployment in duty cycled microsensor nodes. Utilizing a Phase Domain Digital Synthesizer with an FBAR frequency reference, this TX has a start-up latency of just 1.5 mu s. It has been integrated in a 65nm technology and outputs upto 3 dBm power. It achieves a phase noise of -110 dBc/Hz at 1 MHz offset and has a frequency coverage of 2.17 - 2.47 GHz. The power consumption of this TX (including the Digital Baseband) varies from 15 mW at 1.2 Mb/s to 21.4 mW at 51.4 Mb/s. At peak data rate, this leads to an Duty-Cycling-Energy/bit (which takes into account the start-up energy) of 500 pJ/b for transmitting packets of length 32 bytes. Moreover, the TX incorporates a Hybrid Requantizer circuit which helps to trade off in-band noise with the spurs due to the non-linearity induced Sigma Delta noise folding.


Published in:
Esscirc Conference 2016, 129-132
Presented at:
46th European Solid-State Device Research Conference (ESSDERC) / 42nd European Solid-State Circuits Conference (ESSCIRC), Lausanne, SWITZERLAND, SEP 12-15, 2016
Year:
2016
Publisher:
New York, Ieee
ISSN:
1930-8833
ISBN:
978-1-5090-2972-3
Keywords:
Laboratories:




 Record created 2017-01-24, last modified 2018-09-13


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