Bit-flipping LDPC under noise conditions and its application to Physically Unclonable Functions

A low-density parity check (LDPC) circuit and its properties as a post-processor is proposed for physically unclonable functions (PUFs) applications. PUFs can be realized using process variations or signal noises in SRAM or other PUF circuits, whereas the generated data needs to be processed by error check and correction (ECC) because of their inherent intra-PUF variabilities. The bit-flip LDPC circuits that have been developed in this study reveal compact constructions as well as notable noise tolerances during the ECC calculations. Unlike conventional deterministic post-processing, the LDPC circuits made even under unreliable fabrication conditions keep capable of guaranteeing robustness against noises.


Published in:
2016 Ieee International Symposium On Circuits And Systems (Iscas), 1114-1117
Presented at:
IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, CANADA, MAY 22-25, 2016
Year:
2016
Publisher:
New York, Ieee
ISSN:
0271-4302
ISBN:
978-1-4799-5341-7
Keywords:
Laboratories:




 Record created 2017-01-24, last modified 2018-09-13


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