000224462 001__ 224462
000224462 005__ 20190317000623.0
000224462 02470 $$2ISI$$a000386610400089
000224462 037__ $$aCONF
000224462 245__ $$aSingle-FPGA 3D Ultrasound Beamformer
000224462 269__ $$a2016
000224462 260__ $$bIeee$$c2016$$aNew York
000224462 300__ $$a1
000224462 336__ $$aConference Papers
000224462 520__ $$aIn medical diagnosis, ultrasound (US) imaging is one of the most common, safe, and powerful techniques. Volumetric (3D) US imaging, an emerging technique, is even more attractive than standard 2D imaging, as it allows for imaging without the local presence of a trained sonographer finely positioning the probe. This would be particularly useful in rescue operations, remote areas and developing countries. Unfortunately, present-day 3D imagers are expensive, bulky and power-hungry, confining them to hospitals. There is therefore a strong motivation to develop efficient electronics to enable a portable US platform that is small, cheap, and battery- operated. Beamforming (BF) is the most computationally expensive of 3D imaging. Both commercial [1] and research [2] imagers have dealt with the challenge by reducing the number of receive channels, hence simplifying the computation through the usage of far fewer elements. This comes at the cost of image quality, and the resulting machines are nonetheless still non-portable and expensive. In turn, the bottleneck of the BF process is the calculation of acoustic delays, which requires up to trillions of square roots per second. We propose a drastically more efficient architecture [3]. With geometric considerations, each delay is calculated from a small set of square roots (mapped onto CORDICs), plus two additions. In this demo, we will show the reconstruction of a 2.5M-voxel volume, supporting a transducer with 32×32 receive channels. We have fitted the architecture into a single Kintex UltraScale KU040 [4], which is unprecedented. We also extrapolated the utilization of a 80×80 instance on a Virtex UltraScale XCVU190 [4]. Table I shows the implementation results. Fig. 1 shows our beamformer custom block connected to the other FPGA subsystems. The delay calculation architecture is shown in Fig. 2. The demo setup is presented in Fig. 3, where the 3D beamformer is implemented on the FPGA, while the pre- and post-processing stages are currently performed on Matlab.
000224462 700__ $$aYüzügüler, Ahmet Caner
000224462 700__ $$aSimon, W
000224462 700__ $$aIbrahim, Aya
000224462 700__ $$0241996$$g169841$$aAngiolini, Federico
000224462 700__ $$aArditi, Marcel
000224462 700__ $$0240323$$g115534$$aThiran, Jean-Philippe
000224462 700__ $$aDe Micheli, Giovanni$$g167918$$0240269
000224462 7112_ $$dAugust 29 - September 2, 2016$$cLausanne, Switzerland$$a26th International Conference on Field-Programmable Logic and Applications (FPL)
000224462 773__ $$tProceedings of the 26th International Conference on Field-Programmable Logic and Applications (FPL)
000224462 8564_ $$uhttps://infoscience.epfl.ch/record/224462/files/FPL2016_DemoNight.pdf$$zn/a$$s890561$$yn/a
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000224462 917Z8 $$x112915
000224462 917Z8 $$x245036
000224462 937__ $$aEPFL-CONF-224462
000224462 973__ $$rREVIEWED$$sPUBLISHED$$aEPFL
000224462 980__ $$aCONF