Endurance Management for Resistive Logic-In-Memory Computing Architectures

<i>Resistive Random Access Memory</i> (RRAM) is a promising non-volatile memory technology which enables modern in-memory computing architectures. Although RRAMs are known to be superior to conventional memories in many aspects, they suffer from a low write endurance. In this paper, we focus on balancing memory write traffic as a solution to extend the lifetime of resistive crossbar architectures. As a case study, we monitor the write traffic in a Programmable Logic-in-Memory (PLiM) architecture, and propose an endurance management scheme for it. The proposed endurance-aware compilation is capable of handling different trade-offs between write balance, latency, and area of the resulting PLiM implementations. Experimental evaluations on a set of benchmarks including large arithmetic and control functions show that the standard deviation of writes can be reduced by 86.65% on average compared to a naive compiler, while the average number of instructions and RRAM devices also decreases by 36.45% and 13.67%, respectively.


Published in:
Proceedings of the Design, Automation & Test in Europe (DATE)
Presented at:
Design, Automation & Test in Europe (DATE), Lausanne, Switzerland, March 27-31, 2017
Year:
Mar 31 2017
Publisher:
New York, Ieee
ISBN:
978-3-9815370-9-3
Note:
ERC Cybercare 669354 / SNF MAJesty 200021-169084 / SNF 200021-146600
Laboratories:




 Record created 2017-01-10, last modified 2018-09-13

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