In conventional planar EHBTFETs, the interband tunneling phenomena responsible for the drive current takes place vertically in the section of the channel where top and bottom gates overlap. As a result, the horizontal extent of this overlapping between gates is the limiting factor for both the available band-to-band tunneling area and the occupied wafer space. Hence, any design seeking to increase the horizontal size of the device for boosting the ON current levels would not allow for a restrained surface occupation. In contrast with this, the FinEHBTFET is a very promising structure in terms of scalability due to the decoupling between the tunneling area and the required space in the wafer. However, harmful quantum mechanical confinement effects, such as the appearance of parasitic tunneling leakage contributions, need to be assessed in this type of devices in order to quantify their importance and minimize their impact on the device performance.