Vertical versus lateral tunneling FET non-volatile memory cell

This work reports a comparison of high-k AbO(3)/HfO2/Al2O3 dielectric stack Tunnel FETs with both vertical tunneling and lateral tunneling, as non-volatile memory (NVM) cells. Tunnel FET NVM are fabricated and characterized to evaluate their potential as low power memory operation. These memory cells can be programmed with voltages from -10V to -15V (p type devices) and show extremely stable memory hysteresis up 400K with very low leakage. We experimentally show that, in strong contrast with conventional lateral tunneling TFET, the vertical tunneling TFET based NVM memory has a much higher memory window (V-T shift) due to excellently aligned gate field and tunneling path in the latter case.


Published in:
2016 IEEE Silicon Nanoelectronics Workshop (SNW), 42-43
Presented at:
2016 IEEE Silicon Nanoelectronics Workshop (SNW), Honolulu, HI, USA, 12-13 June 2016
Year:
2016
Publisher:
New York, IEEE
Laboratories:




 Record created 2016-10-17, last modified 2018-09-13


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