GigaRad Total Ionizing Dose and Post-Irradiation Effects on 28 nm Bulk MOSFETs
Nowadays, the large majority of ASICs included in CERN’s Large Hadron Collider (LHC) detector systems are built in a commercial 250 nm CMOS technology. The systems will need a major upgrade around 2020 in order to increase the LHC’s luminosity by a factor of ten. This will require new radiation-tolerant tracking detectors and radiation-tolerant front-end (FE) circuits. More advanced CMOS technologies are expected to withstand high level of total ionizing dose (TID) effects up to 1 Grad over ten years of operation. In this perspective, we have investigated 1 Grad TID levels and post-irradiation effects on nMOSFETs fabricated in a commercial 28 nm bulk CMOS process to assess its potential use for the upgrade of CERN’s LHC systems. Radiation-induced charges building-up in field and gate oxides are expected to degrade the device performance. This oxide and interface traps charge leads to a threshold voltage shift of maximum -80 mV which remains within the process tolerances and a drive current reduction of maximum 25% which remains acceptable for most applications. A degraded subthreshold slope less than 38 mV/dec and radiation-induced DIBL effect as well as free electron carrier mobility reduction are also observed. The leakage current increases by three orders of magnitude. However, despite this significant increase of leakage current, the Ion/Ioff ratio remains larger than three orders of magnitude which should be sufficient for most applications. Post-irradiation annealing recovers part of the overall performance degradation even at room temperature. In order to complete the experimental study, pMOSFETs are currently under investigation.