Approximate 32-Bit Floating-Point Unit Design with 53% Power-Area Product Reduction

The floating-point unit is one of the most common building block in any computing system and is used for a huge number of applications. By combining two state-of-the-art techniques of imprecise hardware, namely Gate-Level Pruning and Inexact Speculative Adder, and by introducing a novel Inexact Speculative Multiplier architecture, three different approximate FPUs and one reference IEEE-754 compliant FPU have been integrated in a 65 nm CMOS process within a low-power multi-core processor. Silicon measurements show up to 27% power, 36% area and 53%power-area product savings compared to the IEEE-754 single-precision FPU. Accuracy loss has been evaluated with a high-dynamic-range image tone-mapping algorithm, resulting in small but non-visible errors with image PSNR value of 90 dB.


Published in:
Proceedings of the 42nd European Solid-State Circuits Conference, 465-468
Presented at:
IEEE 42nd European Solid-State Circuits Conference (ESSCIRC), Lausanne, Switzerland, 2016
Year:
2016
Publisher:
New York, Ieee
ISBN:
978-1-5090-2972-3
Keywords:
Laboratories:




 Record created 2016-09-29, last modified 2018-09-13

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