Design of energy-efficient discrete cosine transform using pruned arithmetic circuits

Inexact circuits and approximate computing have been gaining a lot of interest in order to improve performances and energy efficiency beyond the boundaries of conventional digital circuits. Image and video processing is one of the best candidate for applying such techniques. As one of the key building blocks, Discrete Cosine Transform (DCT) accelerators are investigated using pruned arithmetic circuits. A design methodology is presented in order to optimize both image quality and circuit performances. This work demonstrates that with such technique, savings are possible not only on arithmetic units, but in the entire accelerator hardware. Simulations show up to 12 % area and 10 % power savings with less than 20 dB PSNR degradation compared to the conventional DCT design.


Published in:
2016 Ieee International Symposium On Circuits And Systems (Iscas), 341-344
Presented at:
2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, 22-25 May 2016
Year:
2016
Publisher:
New York, IEEE
ISSN:
0271-4302
ISBN:
978-1-4799-5341-7
Keywords:
Laboratories:




 Record created 2016-09-01, last modified 2018-03-17

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