A Low-Power Correlator for Wakeup Receivers with Algorithm Pruning through Early Termination

A low-complexity, low-power digital correlator for wakeup receivers is presented. With the proposed algorithm, unnecessary computational cycles are dynamically pruned from the correlation using an early threshold check. For the algorithm, we provide a rigorous mathematical analysis for the associated complexity/performance trade-offs. Furthermore, a low overhead hardware architecture with early-termination capability is developed and implemented in a 0.18um CMOS technology. The post layout power analysis shows that the presented architecture can reduce power by up to 32% when compared to the conventional architecture with negligible degradation in detection probability and without degradation in false-alarm probability.


Published in:
2016 Ieee International Symposium On Circuits And Systems (Iscas), 2667-2670
Presented at:
2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, May 22-25, 2016
Year:
2016
Publisher:
New York, Ieee
ISSN:
0271-4302
ISBN:
978-1-4799-5341-7
Keywords:
Laboratories:




 Record created 2016-07-28, last modified 2018-03-17


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