We describe the technology and performance of integrated enhancement/depletion (E/D)-mode n(++) GaN/InAlN/AlN/GaN HEMTs with a self-aligned metal-oxide-semiconductor (MOS) gate structure. An identical starting epi-structure was used for both types of devices without the additional need for a contacts regrowth. The n(++) GaN cap layer was etched away in the gate trenches of the E-mode HEMT while it was left intact for the D-mode HEMT. The plasma etching process was shown to be highly selective between the cap and the InAlN barrier and also to polish the InAlN surface. However, different GaN etching initiation times inside and outside the mesa region were obtained. Gate contacts were isolated using a dielectric layer deposited at low temperature through an e-beam resist to retain the self-aligned approach. Feasibility of the approach for future fast GaN-based mixed-signal electronic circuits was shown by obtaining alternative HEMT threshold voltage values of +0.8 V and -2.6 V, invariant maximal output current of similar to 0.35 A mm(-1) despite large source-to-drain distances and by demonstrating a functional logic invertor.