Simulation, Analysis, and Verification of Substrate Currents for Layout Optimization of Smart Power ICs

Today circuit failures in Smart Power ICs due to substrate couplings are partially addressed during the circuit design phase. The state-of-the-art guidelines for the optimization of parasitic couplings provide mainly qualitative rules, which are difficult to implement and to verify during the design of a complex Smart Power circuit. These rules are often based on the physical device simulations or on the empirical results extracted from predefined benchmark structures. In this paper, a novel approach is proposed for designing robust circuits integrating accurate and specific analysis of substrate couplings already into the design flow. First, substrate currents injected by power transistors are discussed to show the spatial distribution of voltage and currents into the substrate. A set of guidelines to optimize substrate currents is presented as a summary of the studied test cases. Then, an H-Bridge output driver was implemented in a 0.35-mu m HVCMOS technology to investigate substrate currents by both measurements and simulations. Reverse currents were deliberately injected into the chip to activate substrate lateral and vertical parasitic bipolar junction transistors and measured data closely match circuit simulation results in both cases.

Published in:
IEEE Transactions on Power Electronics, 31, 9, 6586-6595
Piscataway, Institute of Electrical and Electronics Engineers

 Record created 2016-07-19, last modified 2018-03-17

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