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000218888 005__ 20190812205916.0
000218888 020__ $$a978-1-4503-4330-5
000218888 02470 $$2ISI$$a000389301500004
000218888 0247_ $$a10.1145/2950067.2950072$$2doi
000218888 037__ $$aCONF
000218888 245__ $$aInversion optimization in majority-inverter graphs
000218888 260__ $$c2016-06-15$$bIeee$$aNew York
000218888 269__ $$a2016-06-15
000218888 300__ $$a6
000218888 336__ $$aConference Papers
000218888 490__ $$aIEEE International Symposium on Nanoscale Architectures
000218888 500__ $$aERC Cybercare 669354 / SNF 200021-146600
000218888 520__ $$aMany emerging nanotechnologies realize majority gates as primitive building blocks and they benefit from a majority-based synthesis. Recently, <i>Majority-Inverter Graphs</i> (MIGs) have been introduced to abstract these new technologies. We present optimization techniques for MIGs that aim at rewriting the complemented edges of the graph without changing its shape. We demonstrate the performance of our optimization techniques by considering three cases of emerging technology design: semi-custom digital design using <i>Spin Wave Devices</i> (SWDs) and <i>Quantum-Dot Cellular Automata</i> (QCA); and logic in-memory operation within <i>Resistive Random Access Memories</i> (RRAMs). Our experimental results show that SWD and QCA technologies benefit from complemented edges minimization. Area, delay, and power of SWD-based circuits are improved by 13.8%, 21.1%, and 9.2% respectively, while the number of QCA cells in QCA-based circuits can be decreased by 4.9% on average. Reductions of 14.4% and 12.4% in the number of devices and sequential steps respectively can be achieved for RRAMs when the number of nodes with exactly one complemented input is increased during MIG optimization.
000218888 700__ $$g245949$$aTesta, Eleonora$$0249834
000218888 700__ $$g263922$$aSoeken, Mathias$$0249604
000218888 700__ $$aZografos, Odysseas
000218888 700__ $$aAmaru, Luca
000218888 700__ $$aRaghavan, Praveen
000218888 700__ $$aLauwereins, Rudy
000218888 700__ $$aGaillardon, Pierre-Emmanuel
000218888 700__ $$g167918$$aDe Micheli, Giovanni$$0240269
000218888 7112_ $$dJuly 18-20, 2016$$cBeijing, China$$aIEEE/ACM International Symposium on Nanoscale Archituectures (NANOARCH)
000218888 773__ $$q15-20$$tProceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
000218888 8564_ $$zn/a$$yn/a$$uhttps://infoscience.epfl.ch/record/218888/files/2016_nanoarch.pdf$$s431288
000218888 8560_ $$fcarole.burget@epfl.ch
000218888 909C0 $$xU11140$$pLSI1$$0252283
000218888 909CO $$pIC$$ooai:infoscience.tind.io:218888$$qGLOBAL_SET$$pconf$$pSTI
000218888 917Z8 $$x112915
000218888 917Z8 $$x112915
000218888 917Z8 $$x148230
000218888 937__ $$aEPFL-CONF-218888
000218888 973__ $$rREVIEWED$$aEPFL
000218888 980__ $$aCONF