Chip-Level CMOS Co-Integration of ReRAM-Based Non-Volatile Memories

This work reports a technique to fabricate ReRAM crossbar arrays co-integrated with fully finished 180 nm CMOS technology chips. The proposed integration method enables low- cost ReRAM-CMOS integration and allows the rapid prototyping of complete memory systems. We propose to use W plugs, already present as vias in CMOS technology, as the ReRAM bottom electrodes. The resistance switching layer, WOx, is ob- tained by the mask-free rapid thermal oxidation of the W plug surface. With this method, we are able to fabricate 280 nm non- volatile memory devices without any additional high-resolution lithography. The integrated memory devices operate at 300μA, with a high resistance state of 0.6MΩ and low resistance state of 4kΩ. The electrical characteristics confirm the possibility to integrated non-volatile memories on the back-end-of-the-line of standard CMOS chips, enabling low-cost integration of the memory components with the CMOS driving circuitry.


Published in:
2016 12Th Conference On Ph.D. Research In Microelectronics And Electronics (Prime)
Presented at:
IEEE 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME 2016), Lisbon, Portugal, June 27-30, 2016
Year:
2016
Publisher:
New York, Ieee
ISBN:
978-1-5090-0493-5
Keywords:
Laboratories:




 Record created 2016-05-07, last modified 2018-09-13


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