Architectural Modeling of a Single-Sideband Wireline Serial Data Transceiver for Multi-Drop I/O

This paper presents a wireline serial data transceiver (TRX) architecture employing a concept of single-sideband (SSB) modulation to transmit data over a multi-drop (MD) electrical link with deep notches. The proposed TRX utilizes channel notch as a filter to remove one sideband of the power spectrum of the upconverted signal, thereby reducing the bandwidth occupancy by half. After downconversion is performed by a mixer on the receiver (RX) side, the original baseband (BB) signal can be recovered without loss of any information as long as the upconverted signal does not experience severe distortion by other notches. Simulation results show that the proposed TRX can transmit up to 6.4-Gb/s data stream over a reference MD channel of which the first notch is located at 2.5-GHz without any equalization circuit, while conventional TRX with non-return to zero (NRZ) signaling requires CTLE and at least 5-tap DFE for data rate above 5-Gb/s, to open the eye on the receiver side.


Published in:
Proceedings of the IEEE 12th Conference on Ph.D. Research in Microelectronics and Electronics
Presented at:
IEEE 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME 2016), Lisbon, Portugal, June 27-30, 2016
Year:
2016
Publisher:
New York, Ieee
ISBN:
978-1-5090-0493-5
Laboratories:




 Record created 2016-04-29, last modified 2018-03-17

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