A Wideband MDLL with Jitter Reduction Scheme for Forwarded Clock Serial Links in 40 nm CMOS

This paper presents the design and implementation of a multiplying delay-locked loop (MDLL) in 40 nm bulk CMOS process, which can be used as clock and data recovery (CDR) unit in source-synchronous wire-line communications. The MDLL multiplies the reference frequency and delivers differential inphase (I) and quadrature (Q) clocks by generating 8 equally spaced clock phases and combining these phases appropriately. A technique for reducing deterministic jitter (DJ) in MDLL is proposed. The prototype dissipates 1.1-1.8 mW over output frequency range of 2.6-6.4 GHz, while the RMS jitter and I/Q mismatch remain below 3ps rms and 5 degree, respectively, over the entire range. The core size occupies 60x40 um2 silicon area.


Published in:
2016 14Th Ieee International New Circuits And Systems Conference (Newcas)
Presented at:
IEEE 14th International NEWCAS Conference, Vancouver, Canada, 26-29 June
Year:
2016
Publisher:
New York, Ieee
ISSN:
2472-467X
ISBN:
978-1-4673-8900-6
Keywords:
Laboratories:




 Record created 2016-04-26, last modified 2018-03-17


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