Substrate Current Optimization in Smart Power ICs
Safety requirements for modern automotive electronics call for more and more robust power integrated circuits. The mixed-signal IC design flow alone is often no longer capable of tracking possible design failures in complex Smart Power integrated circuits that are caused by substrate current couplings, and consequently, the use of device simulators has become commonplace. Traditionally, for full chip simulations, device simulations are carried out on a simplified model of the substrate. It is, however, not possible to obtain precise results with this approach because IC functionalities are excluded from substrate device co-simulations that are caused by the lack of back annotation of the circuit with the substrate. In this thesis, a novel substrate extraction methodology which is fully compatible with the conventional CAD design tools is investigated. The IC layout and the technological parameters are used to build an equivalent network of the substrate that is made of lumped elements that model parasitic BJTs. The proposed substrate extraction methodology is suitable for any Smart Power technology, including HV-CMOS and BCD processes. The substrate extraction procedure is based on two major steps. First, the IC layout surface is discretized with a novel non-uniform mesh procedure in order to extract model geometrical parameters and at the same time minimize the number of extracted nodes. Then, according to the applied mesh, an equivalent three-dimensional model of the substrate is extracted and back-annotated to the circuit schematic. The overall procedure is designed to be compatible with today's design CAD tools. The methodology was validated with an integrated circuit that was realized with a HV-CMOS 0.35um technology. Experimental measurements of substrate currents due to single or parallel activation of substrate BJTs were reproduced by SPICE simulation, thus confirming the activation of a latch-up in a specific case. To address the general problem of robust IC design, a fast method to monitor substrate currents is also presented. Substrate extraction is performed during the preliminary design phase in order to identify any critical substrate current path and to minimize related risks with a precise placement of protections in an optimal layout floorplan. This approach has also proved to be an efficient tool for designing and characterizing the effectiveness of passive and active protections. The developed methodology precisely and efficiently minimizes substrate couplings in Smart Power ICs. As a result, designs with a high degree of immunity to substrate currents can be achieved rapidly within the design flow, thus avoiding expensive re-designs.
Programme doctoral Microsystèmes et Microélectronique
Faculté des sciences et techniques de l'ingénieur
Institut de génie électrique et électronique
Jury: Dr Jean-Michel Sallese (président) ; Prof. Maher Kayal (directeur de thèse) ; Prof. Pierre-André Farine, Prof. Bernhard Wicht, Dr Paolo D'Abramo (rapporteurs)
Public defense: 2016-4-29
Record created on 2016-04-25, modified on 2016-08-09