A Power-Efficient 3-D On-Chip Interconnect for Multi-Core Accelerators with Stacked L2 Cache

The use of multi-core clusters is a promising option for data-intensive embedded applications such as multi-modal sensor fusion, image understanding, mobile augmented reality. In this paper, we propose a power-efficient 3-D on-chip interconnect for multi-core clusters with stacked L2 cache memory. A new switch design makes a circuit-switched Mesh-of-Tree (MoT) interconnect reconfigurable to support power-gating of processing cores, memory blocks, and unnecessary interconnect resources (routing switch, arbitration switch, inverters placed along the on-chip wires). The proposed 3-D MoT improves the power efficiency up to 77% in terms of energy-delay product (EDP).


Published in:
Proceedings of Design, Automation and Test in Europe (DATE)
Presented at:
Design, Automation and Test in Europe (DATE), Dresden, Germany, March 14-18, 2016
Year:
2016
Publisher:
New York, IEEE
ISBN:
978-3-9815-3707-9
Laboratories:




 Record created 2016-03-17, last modified 2018-11-26

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