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A Power-Efficient 3-D On-Chip Interconnect for Multi-Core Accelerators with Stacked L2 Cache
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A Power-Efficient 3-D On-Chip Interconnect for Mul[...]
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Kang, Kyungsu
et al
main
file(s):
0205
version 1
0205.pdf
[474.08 KB]
27 Jan 2018, 12:50
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