3D integration can alleviate routing congestion, reducing the wirelength and improving performances. Nevertheless, each TSV still occupies non-negligible silicon area: as the number of TSV increases, their effect on the chip routing is detrimental. The reduction in the number of 3D vias obtained with the adoption of serial vertical connections can relieve the routing congestion of the 3D system by reducing the average wirelength. In this paper we explore the impact of the serial approach on the chip routing of a 3D multi processor platform to quantify the achievable wirelength reduction for a range of TSV technologies. The comparison between the serial and the parallel multi-processor configurations shows up to 12.4% wirelength improvement for the serial solution, with serious consequences on routing delay.