Today automotive industry is demanding more and more compact solutions for embedded electronics to be interfaced with vehicles components such as motor drivers, igniters and car communication buses. That is why Smart Power Integrated Circuits (IC) have been developed where high voltage (HV) and low voltage electronics co-exist on the same chip. As a matter of fact, during the operation of HV transistors with inductive loads, electrons and/or holes are injected in the common silicon substrate. These carriers propagate through different wells and can be collected far away from the HV device. The generated parasitic currents can disturb sensitive analog circuits on the surroundings and many times they compromise the functionality of the entire chip. The failure mechanism is often described in terms of parasitic bipolar transistors activated by the injection of minority or majority carriers. However these parasitic devices are strongly dependent on the layout of the IC whereas their electrical characteristics are not known before the chip production. As a consequence, during the analog design flow there are no available solutions to simulate such substrate currents using modern Computer Aided Design (CAD) tools, and this leads to costly redesigns of Smart Power ICs. In this context, the objective of this research is to develop a general substrate modeling strategy to prevent these problems for whatever possible layout or electrical configuration. The proposed solution relies on the extraction of a parasitic distributed network to be simulated in standard circuit simulators. For that purpose three enhanced lumped components are developed: a diode that accounts for minority carriers injection, a resistor used to propagate carriers away in the substrate, and an homojunction that takes care about doping discontinuities effects. These devices are composed of two coupled circuits, the Total Current Circuit (TCC) and the Minority Carrier Circuit (MCC) and they include capacitive and high current effects. Moreover, the proposed modeling methodology can be further extended to other domains such as a self heating and Electrostatic Discharge (ESD) phenomena provided some extensions are done. Once properly calibrated with respect to a given HV technology process, the proposed substrate model has been proved to be effective to predict triggered parasitic current couplings in Smart Power ICs. As a consequence, new protection strategies can be developed to reduce unwanted parasitic effects. This new methodology and its inherent enhanced devices concept compatible with designers CAD tools opens new horizons for Smart Power ICs robust design.