Multilevel-cell phase-change memory modeling and reliability framework

In the modern digital era of big data applications, there is an ever-increasing demand for higher memory capacity that is both reliable and cost effective. In the domain of non-volatile memory systems, Flash-based storage devices have dominated the consumer space for the past 15 years and have also entered the enterprise storage system in the past 2-3 years. However, with Flash memory devices facing serious scalability limits, there is an imminent need to explore the viability of other non-volatile memory technologies that can replace or complement Flash-based storage in the near future. Significant research efforts have been invested by various universities and research organization across the globe into realizing the so-called next-generation memories (NGMs). Phase-change memory is one such technology, which is viewed as the most promising candidate among the emerging technologies. Phase-Change Memory (PCM) technology is not new as the principle of storing information in chalcogenide-based materials was first explored in the 1960s. However, with the predominance of charge-based memory technology (DRAM, Flash storage, etc) thriving thanks to the technological advancements ofmetal-oxide semiconductor field-effect transistor (MOSFET) based devices, it was not until the late 90s that renewed interest in the class of phase-change materials was ignited. This is the same genre of materials as have been widely used in laser driven optical storage (rewritable CDs and DVDs) during the past 20 years or so. Although PCM chips have already been mass-produced by companies like Micron and Samsung, their capacity was limited as they were based on single-level cell (SLC) storage. The primary research focus of this thesis is on increasing the memory capacity by storing more than one bit of information per device, known as multilevel-cell (MLC). Achieving MLC capability is quite challenging, and we disclose some of our significant achievements in the realization of MLC PCM in the past few years. In this thesis, a comprehensive thermoelectric model is proposed for investigating the thermoelectrics physics in PCM device operation. With the increasing role of thermoelectrics at the smaller technology nodes, the proposed model provides valuable insights for a complete understanding of device operation. The model is validated by comparing the simulation results with experimental measurements. The model can also be used for fine-tuning the material properties, device design and geometry to improve the efficacy of these devices. In the second part of the thesis, the dominant reliability concerns in PCM technology are addressed, particularly focusing on MLC operation. We present a readout circuit for PCM specifically designed for drift resilience in MLC operation. Drift resilience is achieved through the use of specific non-resistance-based cell-state metrics which, in contrast to the traditional cell-state metric, i.e., the low-field electrical resistance, have built-in drift robustness. By employing novel MLC-enabling techniques, we succeeded in demonstrating for the first time, reliable 3-bits/cell memory density with a data retention of 1 week at temperatures ranging from 30±C to 80±C on devices that had been pre-cycled one million times.

Leblebici, Yusuf
Stanisavljevic, Milos
Lausanne, EPFL
Other identifiers:
urn: urn:nbn:ch:bel-epfl-thesis6801-0

 Record created 2015-12-30, last modified 2018-01-28

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