000213817 001__ 213817
000213817 005__ 20190317000331.0
000213817 0247_ $$2doi$$a10.1145/2847263.2847314
000213817 037__ $$aCONF
000213817 245__ $$aA Full-Capacity Local Routing Architecture for FPGAs
000213817 269__ $$a2016
000213817 260__ $$c2016
000213817 336__ $$aConference Papers
000213817 520__ $$aReconfigurable systems employ highly-routable local routing architecture to interconnect generic fine-grain logic blocks. Commercial FPGAs employ 50% sparse crossbars rather than fully-connected crossbars in their local routing architecture to trade off between the area and routability of the Logic Blocks (LBs). While the input crossbar provides good routability and logic equivalence for the inputs of the LB, the outputs of the LBs are typically assigned to a physical location. This lack of flexibility brings strong constraints to the global net router. Here, we propose a novel local routing architecture that guarantees full logic equivalence on all input and output pins of the LBs. First, we introduce full-capacity crossbars to interconnect the outputs of the fine-grain Logic Elements (LEs) to the output pins of the LBs. Second, in the local routing, we use a combination of fully- connected and full-capacity crossbars. The full-capacity crossbars are used for the feedback connections in place of the standard fully-connected crossbars to ensure a full routability while reducing the area footprint. Fully-connected crossbars are still employed for the input connections to maintain the logic equivalence of the inputs. As a result, the novel local routing architecture enhances the routability of the LB clusters without any area overhead. By granting the outputs with logic equivalence, the proposed local routing architecture unlocks the full optimization potential of FPGA routers. Architectural simulations show that without any modification on Verilog-to- Routing (VTR) tool suites, when a commercial FPGA architecture is considered and over a wide set of benchmarks, the novel local routing architecture can reduce 10% channel width and 11% routing area with 10% less area×delay×power on average. Therefore, the novel local routing architecture enhances the routability of FPGA, and brings opportunities in realizing larger implementations on a single FPGA chip.
000213817 6531_ $$aFPGA
000213817 6531_ $$acrossbars
000213817 6531_ $$afull-capacity
000213817 6531_ $$alocal routing
000213817 700__ $$0247487$$g214644$$aTang, Xifan
000213817 700__ $$aGaillardon, Pierre-Emmanuel
000213817 700__ $$aDe Micheli, Giovanni$$0240269$$g167918
000213817 7112_ $$dFebruary 21-23, 2016$$cMonterey, California, USA$$a24rd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2016)
000213817 773__ $$tProceedings of the 24rd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2016)
000213817 8564_ $$uhttps://infoscience.epfl.ch/record/213817/files/XT_FPGA16.pdf$$zn/a$$s113887$$yn/a
000213817 909C0 $$xU11140$$0252283$$pLSI1
000213817 909CO $$pIC$$qGLOBAL_SET$$ooai:infoscience.tind.io:213817$$pconf$$pSTI
000213817 917Z8 $$x112915
000213817 917Z8 $$x112915
000213817 917Z8 $$x112915
000213817 917Z8 $$x112915
000213817 937__ $$aEPFL-CONF-213817
000213817 973__ $$rNON-REVIEWED$$sPUBLISHED$$aEPFL
000213817 980__ $$aCONF