Compact modeling of DG-Tunnel FET for Verilog-A implementation

In this work, a compact model based on an analytical closed form solution of the 1D Poisson's equation for a double-gate Tunnel FET is derived. Furthermore, the current levels are estimated by implementing an algorithm based on the Kane's band-to-band tunneling model. A good agreement with numerical simulations for varying device parameters is demonstrated and the advantages and limitations of the modeling approach are investigated and discussed. The model is implemented in a Verilog-A based circuit simulator and basic circuit blocks like an inverter, a 2-bit half adder and a 15 stage ring oscillator are simulated to demonstrate the capabilities of the model. The switching energy of a Tunnel FET based circuit block is studied with Vdd scaling revealing interesting aspects of Tunnel FET circuit behavior.


Published in:
2015 45th European Solid State Device Research Conference (ESSDERC), 40-43
Presented at:
ESSDERC 2015 - 45th European Solid-State Device Research Conference, Graz, Austria, 14-18 September 2015
Year:
2015
Publisher:
IEEE
Laboratories:




 Record created 2015-11-23, last modified 2018-03-17

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