Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters

This work aims at estimating and comparing the power limits of ΔΣ and charge-redistribution successive-approximation register (CR-SAR) analog-to-digital converters (ADCs), in order to identify which topology is the most power-efficient for a target resolution. A power consumption model for mismatch-limited SAR ADCs and for discrete-time (DT) ΔΣ modulators is presented and validated against experimental data. SAR ADCs are found to be the best choice for low-to-medium resolutions, up to roughly 80 dB of dynamic range (DR). At high resolutions, on the other hand, ΔΣ modulators become more power-efficient. This is due to the intrinsic robustness of the ΔΣ modulation principle against circuit imperfections and non-idealities. Furthermore, a comparison of the area occupation of such topologies reveals that, at high resolutions and for a given dynamic range, ΔΣ ADCs result more area-efficient as well. © 2015 IEEE.

Presented at:
IEEE Nordic Circuits and Systems Conference (NORCAS), Oslo, October 2015

 Record created 2015-11-01, last modified 2018-09-13

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