Co-design of ReRAM Passive Crossbar Arrays Integrated in 180nm CMOS Technology

This work presents the co-integration of resistive random access memory crossbars within a 180nm Read-Write CMOS chip. TaO<sub>x</sub>-based ReRAMs have been fabricated and characterized with materials and process steps compatible with the CMOS Back-End-of-the-Line. Two different strategies, consisting in insertion of an Al<sub>2</sub>O<sub>3</sub>tunnel barrier layer and the design of a dedicated CMOS read circuit, have been developed in order to increase the cell high-to-low resistance ratio of a factor of 1000 and to reduce the sneak-path current effects by one order of magnitude. The ReRAM cells have been integrated directly on a standard CMOS foundry chip, enabling low cost ReRAM-CMOS integration. The integrated memories show a set and reset voltages of -1 and 1.3V, respectively. The measured operating voltages are compatible for low-voltage applications.


Published in:
IEEE Journal of Emerging and Selected Topics in Circuits and Systems, 6, 3, 339-351
Year:
2016
Publisher:
Piscataway, Institute of Electrical and Electronics Engineers
ISSN:
2156-3357
Keywords:
Laboratories:


Note: The status of this file is: EPFL only


 Record created 2015-10-28, last modified 2018-12-03

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