000211906 001__ 211906
000211906 005__ 20181116223319.0
000211906 022__ $$a1536-125X
000211906 02470 $$2ISI$$a000364992600020
000211906 0247_ $$2doi$$a10.1109/TNANO.2015.2482359
000211906 037__ $$aARTICLE
000211906 245__ $$aFrom Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires
000211906 269__ $$a2015
000211906 260__ $$bInstitute of Electrical and Electronics Engineers$$c2015
000211906 336__ $$aJournal Articles
000211906 520__ $$aControllable-Polarity Silicon Nanowire Transistors (CP-SiNWFETs) are among the promising candidates to complement or even replace the current CMOS technology in the near future. Polarity control is a desirable property that allows the on-line configuration of the device polarity. CP-SiNWFETs result in smaller and faster logic gates unachievable with conventional CMOS implementations. From a circuit testing point of view, it is unclear if the current CMOS and FinFET fault models are comprehensive enough to model all the defects of CP-SiNWFETs. In this paper, we explore the possible manufacturing defects of this technology through analyzing the fabrication steps and the layout structure of logic gates. Using the obtained defects, we then evaluate their impacts on the performance and the functionality of CP-SiNWFET logic gates. Out of the results, we extend the current fault model to a new a hybrid model, including stuck-at ptype and stuck-at n-type, which can be efficiently used to test the logic circuits in this technology. The newly introduced fault model can be utilized to adequately capture the malfunction behavior of CP logic gates in the presence of nanowire break, bridge and float defects. Moreover, the simulations revealed that the current CMOS test methods are insufficient to cover all faults, i.e., stuck- Open. We proposed an appropriate test method to capture such faults as well.
000211906 6531_ $$afault-model
000211906 6531_ $$acontrollable-polarity silicon nanowires
000211906 6531_ $$adefect
000211906 6531_ $$agate oxide short
000211906 6531_ $$ananotechnology
000211906 700__ $$aGhasemzadeh, Hassan
000211906 700__ $$aGaillardon, Pierre-Emmanuel
000211906 700__ $$0240269$$aDe Micheli, Giovanni$$g167918
000211906 773__ $$j14$$k6$$q1117-1126$$tIEEE Transactions on Nanotechnology
000211906 8564_ $$s1136734$$uhttps://infoscience.epfl.ch/record/211906/files/07277030%282%29.pdf$$yn/a$$zn/a
000211906 909C0 $$0252283$$pLSI1$$xU11140
000211906 909CO $$ooai:infoscience.tind.io:211906$$particle$$pSTI$$pIC$$qGLOBAL_SET
000211906 917Z8 $$x112915
000211906 917Z8 $$x112915
000211906 917Z8 $$x112915
000211906 917Z8 $$x112915
000211906 937__ $$aEPFL-ARTICLE-211906
000211906 973__ $$aEPFL$$rREVIEWED$$sPUBLISHED
000211906 980__ $$aARTICLE