Infoscience

Patent

Method to design network-on-chip (noc)-based communication systems

To tackle the increasing communication complexity of multi-core systems, scalable Networks on Chips (NoCs) are needed to interconnect the processor, memory and hardware cores of the systems. For the use of NoCs to be feasible in today's industrial designs, a custom-tailored, application-specific architecture that satisfies the objectives and constraints of the targeted application domain is required. In this work we present a method for synthesizing such application-specific NoC architectures. This best topology is achieved by a method to design Networks on Chips (NoCs)-based communication system for connecting on-chip components in a multicore system, said system comprising several elements such as processors, hardware blocks, memories, communicating through the communication system, said communication system comprising at least switches, said method comprising the steps of: - obtaining predefined communication characteristics modelling the applications running on the multicore system, - establishing the number and configuration of switches to connect the elements, - establishing physical connectivity between the elements and the switches, - for each of at least two pairs of communicating elements : a defining a communication path, that is, a sequence of switches to be traversed to connect the aforementioned pair of communicating elements, b calculating metrics as affected by the need to render said path into physical connectivity, said metrics being selected among one or a combination of power consumption of the involved switches, area of the involved switches, number of inputs and outputs of the involved switches, total length of wires used, maximum possible speed of operation of the system and number of switches to be traversed, taking into account any previously defined physical connectivity, c iterating the steps a and b for a plurality of possible paths, d choosing the path having the optimal metrics, e establishing any missing physical connectivity between the switches so that the selected optimal path occurs across physically connected switches.

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