Iterative Layering: Optimizing arithmetic circuits by structuring the information flow
2009
Details
Title
Iterative Layering: Optimizing arithmetic circuits by structuring the information flow
Author(s)
Verma, Ajay K. ; Brisk, Philip ; Ienne, Paolo
Published in
Proceedings of the International Conference on Computer Aided Design
Pages
797-804
Conference
International Conference on Computer Aided Design, San Jose, California, USA
Date
2009
ISBN
978-1-60558-800-1
Laboratories
LAP
Record Appears in
Scientific production and competences > I&C - School of Computer and Communication Sciences > IINFCOM > LAP - Processor Architecture Laboratory
Peer-reviewed publications
Conference Papers
Work produced at EPFL
Published
Peer-reviewed publications
Conference Papers
Work produced at EPFL
Published
Record creation date
2015-08-31