Automatic Generation of Inexact Digital Circuits by Gate-level Pruning

Inexact or approximate circuits show great ability to reduce power consumption at the cost of occasional errors in comparison to their conventional counterparts. Even though the benefits of such circuits have been proven for many applications, they are not wide spread owing to the absence of a clear design methodology and the required CAD tools. In this regard, this paper presents a methodology to automatically generate inexact circuits starting from a conventional design by adding only one small step in the digital design flow. Further, this paper also demonstrates that achieving pruning at gate-level can lead to substantial savings in terms of power consumption, critical path delay and silicon area. An order of magnitude area and power savings is demonstrated for a 64-bit gate level pruned high-speed adder for a 10% relative error magnitude.

Publié dans:
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 173-176
Présenté à:
2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May 24-27, 2015

 Notice créée le 2015-08-03, modifiée le 2018-01-28

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